1. Field of the Invention
The invention relates to a semiconductor device, and more particularly to a new high-side device integrated with an original low-side device.
2. Description of the Related Art
A variety of power suppliers and motor drivers utilize bridge circuits to control a power source to a load. The bridge circuit normally has a high-side transistor connected to the power source and a low-side transistor connected to the ground. A common node between the high-side transistor and the low-side transistor is coupled to the load. As the transistors are controlled to alternately conduct, the voltage of the common node swings between voltage levels of the power source and the ground. Therefore, a high-side transistor driver requires a charge pump circuit and/or a floating drive circuit in order to fully turn on the high-side transistor. In recent development, many floating circuits are being disclosed in U.S. Pat. No. 6,344,959 (Milazzo), U.S. Pat. No. 6,781,422 (Yang) and U.S. Pat. No. 6,836,173 (Yang).
FIG. 1 shows a high-side transistor drive circuit. A floating circuit 10 is applied to control the on/off state of a high-side transistor 11. An NMOS transistor 12 is connected to receive a control signal S1 through an inverter 13 in a low-side circuit. The NMOS transistor 12 comprises a drain region 120 coupled to an inverter 17 of the floating circuit 10. The high-side transistor 11 is coupled to a low-side transistor 14 at a common node where an output voltage VO is generated. A charge-pump capacitor 15 provides a supply voltage to the floating circuit 10. A voltage VD charges the charge-pump capacitor 15 through a diode 16 once the low-side transistor 14 is turned on according to a control signal S2. The ground reference of the charge-pump capacitor 15 is pulled to the level of a voltage source VIN when the high-side transistor 11 is turned on.
FIG. 2 shows a top view of a conventional semiconductor device of the high-side inverter 17 and the low-side inverter 13 shown in FIG. 1. The integrated circuit includes a high-side region 2 to form high-side devices, such as the high-side inverter 17. A barrier 170 is disposed between the high-side region 2 and a low-side region 3.
The drain region 120 of the NMOS transistor 12 is coupled to an NMOS transistor 20 and a PMOS transistor 21 of the high-side region 2 through a high-side conduction line 22, and a gate region of the NMOS transistor 12 is coupled to an NMOS transistor 30 and a PMOS transistor 31 of the low-side region 3.
FIG. 3 shows a cross view of a conventional semiconductor structure of the semiconductor device shown in FIG. 2. The NMOS transistor 12 is disposed in an N-type well 102. An N+ conductivity type region forms the drain region (D) 120, another N+ conductivity type region forms a source region (S) 121, and a poly-silicon material between the drain region 120 and the source region 121 forms a gate electrode (G) 122. Wherein the gate electrode 122 is disposed above oxides 123 for controlling the current flow in the conduction channel. The high-side devices comprise the NMOS transistor 20 and the PMOS transistor 21 to serve as the high-side inverter 17. In the NMOS transistor 20, an N+ conductivity type region is disposed in a P-type well 204 as a source region (S) 200, another N+ conductivity type region disposed in an N-type region 201 (N-type Double diffusion region, wherein the N+ conductivity type region has a heavy diffusion concentration, and the N-type region 201 has a light diffusion concentration) forms a drain region (D) 202, and a poly-silicon material between the drain region 202 and the source region 200 forms a gate electrode (G) 203. For the PMOS transistor 21, a P+ conductivity type region is disposed in the N-type well 102 as a source region (S) 210, another P+ conductivity type region disposed in a P-type region 211(P-type Double diffusion region, wherein the P+ conductivity type region has a heavy diffusion concentration, and the P-type region 211 has a light diffusion concentration) forms a drain region (D) 212, and a poly-silicon material between the drain region 212 and the source region 210 forms a gate electrode (G) 213. The P-type well barrier 170 is composed of a P+ conductivity type region 171. A P diffusion region 172 is disposed in the N-type well 102. The high-side conduction line (500V) 22 is coupled across the P-type well barrier 170.
The low-side devices comprise the NMOS transistor 30 and the PMOS transistor 31 to serve as the low-side inverter 13. The NMOS transistor 30 and the PMOS transistor 31 are disposed in the deep N-type well 102. The NMOS transistor 30 comprises an N+ conductivity type region as a drain region (D) 40, and another N+ conductivity type region disposed in a P-type well 41 as a source region (S) 42. A poly-silicon material between the drain region 40 and the source region 42 forms a gate electrode (G) 43. The PMOS transistor 31 comprises a P+ conductivity type region as a source region (S) 50, and another P+ conductivity type region disposed in a P-type well 51 as a drain region (D) 52. A poly-silicon material between the drain region 52 and the source region 50 forms a gate electrode 53.
The drawback of the conventional semiconductor structure is that the operation voltage of the high-side conduction line is lower because dielectric breakdown voltage between high-side conduction line 22 and the metal of the barrier 170 (Metal-to-Metal dielectric breakdown voltage) is 500 V. The operation voltage of the NMOS transistor 20 is 15V. Higher dielectric breakdown voltage and operation voltage is appreciated.